Texas Instruments SN74LVC1G125DBVR Bus Buffer, 5-Pin SOT-23
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4 ns @ 5 V
Dimensions
2.9 x 1.6 x 1.15mm
Maximum Operating Supply Voltage
5.5 V
Height
1.15mm
Propagation Delay Test Condition
50pF
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Width
1.6mm
Length
2.9mm
Maximum Operating Temperature
+85 °C
Country of Origin
China
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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AED 7.88
AED 0.315 Each (In a Pack of 25) (ex VAT)
AED 8.27
AED 0.331 Each (In a Pack of 25) (inc. VAT)
25
AED 7.88
AED 0.315 Each (In a Pack of 25) (ex VAT)
AED 8.27
AED 0.331 Each (In a Pack of 25) (inc. VAT)
Stock information temporarily unavailable.
25
Stock information temporarily unavailable.
| Quantity | Unit price | Per Pack |
|---|---|---|
| 25 - 100 | AED 0.315 | AED 7.88 |
| 125 - 225 | AED 0.262 | AED 6.56 |
| 250 - 350 | AED 0.262 | AED 6.56 |
| 375 - 600 | AED 0.21 | AED 5.25 |
| 625+ | AED 0.21 | AED 5.25 |
Ideate. Create. Collaborate
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Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4 ns @ 5 V
Dimensions
2.9 x 1.6 x 1.15mm
Maximum Operating Supply Voltage
5.5 V
Height
1.15mm
Propagation Delay Test Condition
50pF
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Width
1.6mm
Length
2.9mm
Maximum Operating Temperature
+85 °C
Country of Origin
China
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
Ideate. Create. Collaborate
JOIN FOR FREE
No hidden fees!
- Download and use our DesignSpark software for your PCB and 3D Mechanical designs
- View and contribute website content and forums
- Download 3D Models, Schematics and Footprints from more than a million products