Technical Documents
Specifications
Brand
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
18V
Minimum Operating Temperature
-55°C
Maximum Operating Temperature
125°C
Length
10mm
Height
1.5mm
Standards/Approvals
No
Series
4000B
Automotive Standard
AEC-Q100
Product Details
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
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Stock information temporarily unavailable.
AED 92.45
AED 1.926 Each (In a Tube of 48) (ex VAT)
AED 97.07
AED 2.022 Each (In a Tube of 48) (inc. VAT)
48
AED 92.45
AED 1.926 Each (In a Tube of 48) (ex VAT)
AED 97.07
AED 2.022 Each (In a Tube of 48) (inc. VAT)
Stock information temporarily unavailable.
48
| Quantity | Unit price | Per Tube |
|---|---|---|
| 48 - 432 | AED 1.926 | AED 92.45 |
| 480 - 912 | AED 1.444 | AED 69.34 |
| 960+ | AED 1.284 | AED 61.63 |
Ideate. Create. Collaborate
JOIN FOR FREE
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Technical Documents
Specifications
Brand
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
18V
Minimum Operating Temperature
-55°C
Maximum Operating Temperature
125°C
Length
10mm
Height
1.5mm
Standards/Approvals
No
Series
4000B
Automotive Standard
AEC-Q100
Product Details
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
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JOIN FOR FREE
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